A digital circuit can include a delay component that can adjust timings of the digital circuit to optimize circuit performances. For example, a digital circuit may include a plurality of internal clock signals that can be generated based directly or indirectly on a reference clock signal. The plurality of clock signals may have significant skews due to, for example, different propagation delays from the reference clock signal. A clock skew may adversely affect a circuit performance. To optimize the circuit performance, a delay component can be used to compensate for the clock skew. In another example, a circuit operation may require a specific timing sequence of multiple signals, such as clock signals, control signals, and the like. The specific timing sequence can be enabled by suitably applying delay components to the multiple signals.